IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Fully Pipelined Multiplierless Architecture for 2D Convolution with Quadrant Symmetric Kernels

APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): M.Z. Zhang ; V.K. Asari
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2006
Conference Location: Singapore, Singapore
Conference Date: 4 December 2006
Page(s): 1,559 - 1,562
ISBN (Paper): 1-4244-0387-1
DOI: 10.1109/APCCAS.2006.342541
Regular:

Design of a fully pipelined multiplierless digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants... View More

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