IEEE - Institute of Electrical and Electronics Engineers, Inc. - A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter

APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Yi-Chih Chao ; Ji-Kun Lin ; Jar-Ferr Yang ; Bin-Da Liu
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2006
Conference Location: Singapore, Singapore
Conference Date: 4 December 2006
Page(s): 1,260 - 1,263
ISBN (Paper): 1-4244-0387-1
DOI: 10.1109/APCCAS.2006.342392
Regular:

In this paper, we propose a high throughput and data reuse architecture for de-blocking filter in H.264/AVC. There are two SRAMs exploited in the design. One is 144times32 bits single-port SRAM,... View More

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