IEEE - Institute of Electrical and Electronics Engineers, Inc. - Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits

APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): B.A. Rosdi ; A. Takahashi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2006
Conference Location: Singapore, Singapore
Conference Date: 4 December 2006
Page(s): 801 - 804
ISBN (Paper): 1-4244-0387-1
DOI: 10.1109/APCCAS.2006.342142
Regular:

A new algorithm is proposed to reduce the area of a pipelined circuit using a combination of multi-clock cycle paths, clock scheduling and delay balancing. The algorithm analyzes the circuit and... View More

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