IEEE - Institute of Electrical and Electronics Engineers, Inc. - VLSI Architecture for High-Speed / Low-Power Implementation of Multilevel Lifting DWT

APCCAS 2006. 2006 IEEE Asia Pacific Conference on Circuits and Systems

Author(s): Basant K. Mohanty ; Pramod K. Meher
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 December 2006
Conference Location: Singapore, Singapore
Conference Date: 4 December 2006
Page(s): 458 - 461
ISBN (Paper): 1-4244-0387-1
DOI: 10.1109/APCCAS.2006.342488
Regular:

In this paper, we propose a pipeline architecture for VLSI implementation of multilevel lifting-based discrete wavelet transform (DWT). The proposed architecture can compute multilevel lifting DWT... View More

Advertisement