IEEE - Institute of Electrical and Electronics Engineers, Inc. - Multiple Fault Models for Timed FSMs

IEEE Instrumentation and Measurement Technology Conference

Author(s): S.S. Batth ; M.U. Uyar ; Yu Wang ; M.A. Fecko
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 April 2006
Conference Location: Sorrento, Italy
Conference Date: 24 April 2006
Page(s): 936 - 941
ISBN (CD): 0-7803-9360-0
ISBN (Paper): 0-7803-9359-7
ISSN (Paper): 1091-5281
DOI: 10.1109/IMTC.2006.328260
Regular:

An implementation under test (IUT) can be formally described using finite-state machines (FSMs). Due to the presence of inherent timing constraints and variables in a communication protocol, an... View More

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