IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties

11th IEEE International High Level Design Validation and Test Workshop

Author(s): M. Boule ; Z. Zilic
Sponsor(s): IEEE Comput. Soc. Test Technol. Tech. Council
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2006
Conference Location: Monterey, CA, USA
Conference Date: 8 November 2006
Page(s): 69 - 76
ISBN (CD): 1-4244-0680-3
ISBN (Paper): 1-4244-0679-X
ISSN (Paper): 1552-6674
DOI: 10.1109/HLDVT.2006.319966
Regular:

Automata-based methods for generating PSL hardware assertion checkers were primarily considered for use with temporal sequences, as opposed to full-scale properties. We present a technique for... View More

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