IEEE - Institute of Electrical and Electronics Engineers, Inc. - High Performance 65nm SOI Transistors Using Laser Spike Annealing

ESSDERC 2006. Proceedings of the 36th European Solid-State Device Research Conference

Author(s): T. Yamashita ; P.A. Fisher ; O. Gluschenkov ; H. Kimura ; R. Ramachandran ; A.C. Mocuta ; J. Kluth ; T. Kawamura ; K. Onishi ; D. Fried ; S. Narasimha ; D. Brown ; Sameer Jain ; K. Miyamoto ; G. Freeman ; S.V. Deshpande ; S. Luning ; Shih-Fen Huang ; J. Pellerin ; H. Kuroda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2006
Conference Location: Montreux, Switzerland
Conference Date: 19 September 2006
Page(s): 347 - 350
ISBN (Paper): 1-4244-0301-4
ISSN (Electronic): 2378-6558
ISSN (Paper): 1930-8876
DOI: 10.1109/ESSDER.2006.307709
Regular:

In this paper we present enhancements in transistor performance and manufacturability of a high performance 65nm node SOI transistor by the combination of reduced RTA temperature and laser spike... View More

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