IEEE - Institute of Electrical and Electronics Engineers, Inc. - New Floating Gate Self-Aligning Technology for Multilevel NOR Flash Memory

ESSDERC 2006. Proceedings of the 36th European Solid-State Device Research Conference

Author(s): W.H. Lee ; Jae-Hoon Kim ; Ki-Yeol Byun ; Bong-Yong Lee ; Sang-Pil Sim ; Chan-Kwang Park ; Kinam Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2006
Conference Location: Montreux, Switzerland
Conference Date: 19 September 2006
Page(s): 218 - 221
ISBN (Paper): 1-4244-0301-4
ISSN (Paper): 1930-8876
DOI: 10.1109/ESSDER.2006.307677
Regular:

This paper describes the key technology to realize a scaled multilevel NOR flash memory with an improved gate oxide integrity. It is found that a thin poly-Si employed in STI formation is a good... View More

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