IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Low-Jitter and Low-Power CMOS PLL for Clock Multiplication

ESSCIRC 2006. Proceedings of the 32nd European Solid-State Circuits Conference

Author(s): Xintian Shi ; K. Imfeld ; S. Tanner ; M. Ansorge ; P.-A. Farine
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2006
Conference Location: Montreux, Switzerland
Conference Date: 19 September 2006
Page(s): 174 - 177
ISBN (Paper): 1-4244-0303-0
ISSN (Paper): 1930-8833
DOI: 10.1109/ESSCIR.2006.307559
Regular:

This paper describes a phase-locked loop (PLL) designed for clock multiplication in a LVDS transmitter. The PLL consists of a novel low-jitter charge-pump, a fully differential ring-oscillator... View More

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