IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of phosphorous pile-up at the Si/SiO/sub 2/ interface

2006 8th International Conference on Solid-State and Integrated Circuit Technology

Author(s): A. Seike ; I. Sano ; K. Yamada ; I. Ohdomari
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Shanghai, China
Conference Date: 23 October 2006
Page(s): 2,172 - 2,174
ISBN (CD): 1-4244-0161-5
ISBN (Paper): 1-4244-0160-7
DOI: 10.1109/ICSICT.2006.306672
Regular:

As we all know from the famous prediction for the micron order transistor era, which Gordon Moore predicted, the performance of transistors improved exponentially, but it doesn't quite follow his... View More

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