IEEE - Institute of Electrical and Electronics Engineers, Inc. - A High-Speed Area-Efficient Architecture for the Arithmetic in GF(2m)

2006 8th International Conference on Solid-State and Integrated Circuit Technology

Author(s): Jian Wang ; Anping Jiang
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Shanghai, China
Conference Date: 23 October 2006
Page(s): 2,016 - 2,018
ISBN (CD): 1-4244-0161-5
ISBN (Paper): 1-4244-0160-7
DOI: 10.1109/ICSICT.2006.306579
Regular:

Finite fields have been used for numerous applications including error-control coding and cryptography. This paper presents a high-speed area-efficient architecture for arithmetic that can support... View More

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