IEEE - Institute of Electrical and Electronics Engineers, Inc. - VLSI Implementation of Low Power High Throughput Low Density Parity Check Code Decoder for Optical Communication

2006 Annual IEEE India Conference

Author(s): Kaushik Vaidyanathan ; Anusha Radhakrishnan ; Valli Sounthariya Kumar ; K. Kannan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2006
Conference Location: New Delhi, India
Conference Date: 15 September 2006
Page(s): 1 - 5
ISBN (CD): 1-4244-0370-7
ISBN (Paper): 1-4244-0369-3
ISSN (Electronic): 2325-9418
ISSN (Paper): 2325-940X
DOI: 10.1109/INDCON.2006.302827
Regular:

In this paper we propose a novel architecture with an adaptive approach to the existing partly parallel joint code and decoder design methodology for low density parity check (LDPC) codes. The low... View More

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