IEEE - Institute of Electrical and Electronics Engineers, Inc. - Design of High-Speed-Pipelined Execution Unit of 32-bit RISC Processor

2006 Annual IEEE India Conference

Author(s): S. Islam ; D. Chattopadhyay ; M. Kumar Das ; V. Neelima ; S. Sarkar
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 September 2006
Conference Location: New Delhi, India
Conference Date: 15 September 2006
Page(s): 1 - 5
ISBN (CD): 1-4244-0370-7
ISBN (Paper): 1-4244-0369-3
ISSN (Electronic): 2325-9418
ISSN (Paper): 2325-940X
DOI: 10.1109/INDCON.2006.302780
Regular:

The paper describes the architecture and design of the pipelined execution unit of a 32-bit RISC processor. Organization of the blocks in different stages of pipeline is done in such a way that... View More

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