IEEE - Institute of Electrical and Electronics Engineers, Inc. - Throughput optimization via cache partitioning for embedded multiprocessors

2006 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Author(s): A.M. Molnos ; S.D. Cotofana ; M.J.M. Heijligers ; J.T.J. van Eijndhoven
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2006
Conference Location: Samos, Greece
Conference Date: 17 July 2006
Page(s): 185 - 191
ISBN (Paper): 1-4244-0155-0
DOI: 10.1109/ICSAMOS.2006.300826
Regular:

In embedded multiprocessors cache partitioning is a known technique to eliminate inter-task cache conflicts, so to increase predictability. On such systems, the partitioning ratio is a parameter... View More

Advertisement