IEEE - Institute of Electrical and Electronics Engineers, Inc. - Accelerating RTL Simulation by Several Orders of Magnitude Using Clock Suppression

2006 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Author(s): H. Muhr ; R. Holler
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2006
Conference Location: Samos, Greece
Conference Date: 17 July 2006
Page(s): 123 - 128
ISBN (Paper): 1-4244-0155-0
DOI: 10.1109/ICSAMOS.2006.300818
Regular:

In recent years designers of embedded computer systems face a tremendous growth in complexity of their systems. This, together with the fact that the used system clock frequencies rise and that... View More

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