IEEE - Institute of Electrical and Electronics Engineers, Inc. - Chip Size Estimation for SOC Design Space Exploration

2006 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation

Author(s): H. Jeschke
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 July 2006
Conference Location: Samos, Greece
Conference Date: 17 July 2006
Page(s): 56 - 62
ISBN (Paper): 1-4244-0155-0
DOI: 10.1109/ICSAMOS.2006.300809
Regular:

At early design space exploration phases of architectures for systems on a chip (SOC) total costs of silicon are of high interest. An accurate chip size estimation needs detailed knowledge of the... View More

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