IEEE - Institute of Electrical and Electronics Engineers, Inc. - Scheduler Optimization by Exploring Wakeup Locality

2006 International Conference on Computer Engineering & Systems

Author(s): Kuo-Su Hsiao ; Chung-Ho Chen
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 November 2006
Conference Location: Cairo, Egypt
Conference Date: 5 November 2006
Page(s): 115 - 120
ISBN (CD): 1-4244-0272-7
ISBN (Paper): 1-4244-0271-9
DOI: 10.1109/ICCES.2006.320434
Regular:

In a high-performance superscalar processor, the instruction scheduler often comes with poor scalability and high complexity due to the expensive instruction wakeup operation. Using detailed... View More

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