IEEE - Institute of Electrical and Electronics Engineers, Inc. - SOC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?

2006 IEEE International Test Conference

Author(s): M. Genden
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2006
Conference Location: Santa Clara, CA, USA
Conference Date: 22 October 2006
Page(s): 1
ISBN (CD): 1-4244-0292-1
ISBN (Paper): 1-4244-0291-3
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.2006.297762
Regular:

Traditionally, developers of multi-core chips have relied upon system-level techniques such as boundary scan and external instrumentation to access internal signals during silicon debug. The... View More

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