IEEE - Institute of Electrical and Electronics Engineers, Inc. - SOC and Multi-Core Debug: Are Design for Debug (DFD) features that are put in reuse cores sufficient for Silicon Debug?
2006 IEEE International Test Conference
|Publisher:||IEEE - Institute of Electrical and Electronics Engineers, Inc.|
|Publication Date:||1 October 2006|
|Conference Location:||Santa Clara, CA, USA|
|Conference Date:||22 October 2006|
Traditionally, developers of multi-core chips have relied upon system-level techniques such as boundary scan and external instrumentation to access internal signals during silicon debug. The... View More
Traditionally, developers of multi-core chips have relied upon system-level techniques such as boundary scan and external instrumentation to access internal signals during silicon debug. The system-on-a-chip (SoC) nature of the cell processor makes it more difficult to rely on these techniques, as the system bus is internal to the chip, and only a limited number of pins are accessible. The cell development team was thus presented with the challenge of designing a sufficient built-in facility that could provide visibility to critical nodes within cell's multiple partitions. The team answered this challenge with the design of cell's centralized trace logic analyzer. The cell trace logic analyzer is a powerful built-in tool that allows for debug and analysis of processor components by providing a window to internal signals. Its main components are the debug bus, match logic, state control logic, and trace array. The centralized approach allows for a high degree of user programmability and flexibility that would not otherwise be feasible under typical design constraintsView Less