IEEE - Institute of Electrical and Electronics Engineers, Inc. - An Enhanced EDAC Methodology for Low Power PSRAM

2006 IEEE International Test Conference

Author(s): Po-Yuan Chen ; Yi-Ting Yeh ; Chao-Hsun Chen ; Jen-Chieh Yeh ; Cheng-Wen Wu ; Jeng-Shen Lee ; Yu-Chang Lin
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2006
Conference Location: Santa Clara, CA, USA
Conference Date: 22 October 2006
Page(s): 1 - 10
ISBN (CD): 1-4244-0292-1
ISBN (Paper): 1-4244-0291-3
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.2006.297689
Regular:

As feature size keeps shrinking, how to maintain the reliability becomes an important issue in IC production, especially for high density memory circuits. Error detection and correction (EDAC)... View More

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