IEEE - Institute of Electrical and Electronics Engineers, Inc. - Efficient Latch and Clock Structures for System-on-Chip Test Flexibility

2006 IEEE International Test Conference

Author(s): D.E. Lackey
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 October 2006
Conference Location: Santa Clara, CA, USA
Conference Date: 22 October 2006
Page(s): 1 - 7
ISBN (CD): 1-4244-0292-1
ISBN (Paper): 1-4244-0291-3
ISSN (Paper): 1089-3539
DOI: 10.1109/TEST.2006.297657
Regular:

This paper describes a novel implementation of edge-triggered flip-flops that incorporates the most optimum features of the leading design-for-testability (DFT) methods in the industry in a... View More

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