IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 1-V 100MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture

2006 Symposium on VLSI Circuits

Author(s): Ying Wu ; V.S.L. Cheung ; H. Luong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 15 June 2006
Page Count: 2
Page(s): 136 - 137
ISBN (Paper): 1-4244-0006-6
DOI: 10.1109/VLSIC.2006.1705347
Regular:

A 1V, 8-bit dual-mode ADC is realized using multi-phase switched-opamp (SO) technique. Employing a proposed loading-free pipelined ADC architecture and a fast-wake-up dual-input-dual-output... View More

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