IEEE - Institute of Electrical and Electronics Engineers, Inc. - Through Silicon Via and 3-D Wafer/Chip Stacking Technology

2006 Symposium on VLSI Circuits

Author(s): K. Takahashi ; M. Sekiguchi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 15 June 2006
Page Count: 4
Page(s): 89 - 92
ISBN (Paper): 1-4244-0006-6
DOI: 10.1109/VLSIC.2006.1705326
Regular:

Through silicon via and 3D wafer/chip stacking technology is thought to be the essential technology of the next generation high-end semiconductors such as high-speed microprocessors and high-speed... View More

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