IEEE - Institute of Electrical and Electronics Engineers, Inc. - PLL On-Chip Jitter Measurement: Analysis and Design

2006 Symposium on VLSI Circuits

Author(s): S.D. Vamvakos ; V. Stojanovic ; J.L. Zerbe ; C.W. Werner ; D. Draper ; B. Nikolic
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 15 June 2006
Page Count: 2
Page(s): 73 - 74
ISBN (Paper): 1-4244-0006-6
DOI: 10.1109/VLSIC.2006.1705318
Regular:

Analysis of on-chip jitter measurements based on the dead-zone method reveals potentially large errors in the jitter variance estimate, when the jitter distribution is changing or not known a... View More

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