IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Vth-Variation-Tolerant SRAM with 0.3-V Minimum Operation Voltage for Memory-Rich SoC Under DVS Environment

2006 Symposium on VLSI Circuits

Author(s): Y. Morita ; H. Fujiwara ; H. Noguchi ; K. Kawakami ; J. Miyakoshi ; S. Mikami ; K. Nii ; H. Kawaguchi ; M. Yoshimoto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 15 June 2006
Page Count: 2
Page(s): 13 - 14
ISBN (Paper): 1-4244-0006-6
DOI: 10.1109/VLSIC.2006.1705288
Regular:

This paper proposes a voltage-control scheme for an SRAM that makes a minimum operation voltage down to 0.3 V even on a future memory-rich SoC. A self-aligned timing control guarantees stable... View More

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