IEEE - Institute of Electrical and Electronics Engineers, Inc. - Advanced Junction Profile Engineering Featuring Laser Spike Annealing and Co-Implantation for Sub-30-nm Strained CMOS Devices

2006 Symposium on VLSI Technology

Author(s): T. Yamamoto ; T. Kubo ; T. Sukegawa ; K. Hashimoto ; M. Kase
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 13 June 2006
Page Count: 2
Page(s): 186 - 187
ISBN (Paper): 1-4244-0005-8
DOI: 10.1109/VLSIT.2006.1705279
Regular:

We have developed a novel junction profile engineering using laser spike annealing (LSA) with co-implant and applied it to sub-30-nm strained CMOS devices. A 55% reduction in source-drain... View More

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