IEEE - Institute of Electrical and Electronics Engineers, Inc. - Sub-5nm All-Around Gate FinFET for Ultimate Scaling

2006 Symposium on VLSI Technology

Author(s): Hyunjin Lee ; Lee-Eun Yu ; Seong-Wan Ryu ; Jin-Woo Han ; Kanghoon Jeon ; Dong-Yoon Jang ; Kuk-Hwan Kim ; Jiye Lee ; Ju-Hyun Kim ; Sang Cheol Jeon ; Gi Seong Lee ; Jae Sub Oh ; Yun Chang Park ; Woo Ho Bae ; Hee Mok Lee ; Jun Mo Yang ; Jung Jae Yoo ; Sang Ik Kim ; Yang-Kyu Choi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 13 June 2006
Page Count: 2
Page(s): 58 - 59
ISBN (Paper): 1-4244-0005-8
DOI: 10.1109/VLSIT.2006.1705215
Regular:

Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at... View More

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