IEEE - Institute of Electrical and Electronics Engineers, Inc. - Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering

2006 Symposium on VLSI Technology

Author(s): J. Kavalieros ; B. Doyle ; S. Datta ; G. Dewey ; M. Doczy ; B. Jin ; D. Lionberger ; M. Metz ; W. Rachmady ; M. Radosavljevic ; U. Shah ; N. Zelick ; R. Chau
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Honolulu, HI, USA
Conference Date: 13 June 2006
Page Count: 2
Page(s): 50 - 51
ISBN (Paper): 1-4244-0005-8
DOI: 10.1109/VLSIT.2006.1705211
Regular:

We have combined the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering. High performance NMOS and PMOS... View More

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