IEEE - Institute of Electrical and Electronics Engineers, Inc. - Formal Modelling and Verification of an Asynchronous DLX Pipeline

Fourth IEEE International Conference on Software Engineering and Formal Methods

Author(s): H.K. Kapoor
Sponsor(s): IEEE Comput. Soc
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Pune, India
Conference Date: 11 September 2006
Page(s): 118 - 127
ISBN (Paper): 0-7695-2678-0
DOI: 10.1109/SEFM.2006.18
Regular:

A five stage pipeline of an asynchronous DLX processor is modelled and its control flow is verified. The model is built using an asynchronous pipeline of latches separated by processing logic. We... View More

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