IEEE - Institute of Electrical and Electronics Engineers, Inc. - Speeding Up Sequential Simulated Annealing by Parallelization

International Symposium on Parallel Computing in Electrical Engineering

Author(s): Z.J. Czech
Sponsor(s): IEEE CSP
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Bialystok, Poland
Conference Date: 13 September 2006
Page(s): 349 - 356
ISBN (Paper): 0-7695-2554-7
DOI: 10.1109/PARELEC.2006.74
Regular:

A parallel algorithm of simulated annealing to solve the vehicle routing problem with time windows (VRPTW) is considered. The VRPTW is an NP-hard bicriterion optimization problem in which both the... View More

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