IEEE - Institute of Electrical and Electronics Engineers, Inc. - FPGA Chip as a System Master for Hardware Aided Parallel Computing

International Symposium on Parallel Computing in Electrical Engineering

Author(s): J. Pierzchlewski ; P. Sniatala ; B. Nowakowski ; A. Rybarczyk ; W. Wencel
Sponsor(s): IEEE CSP
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Bialystok, Poland
Conference Date: 13 September 2006
Page(s): 220 - 226
ISBN (Paper): 0-7695-2554-7
DOI: 10.1109/PARELEC.2006.39
Regular:

This paper presents prototype board and its operating system dedicated for application specific parallel processing. The proposed architecture consists of two AVR microprocessors, FPGA Spartan3,... View More

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