IEEE - Institute of Electrical and Electronics Engineers, Inc. - Evaluation of On-Chip Interfaces for Dynamically Reconfigurable Coprocessors

International Symposium on Parallel Computing in Electrical Engineering

Author(s): B. Griese ; B. Kettelhoit ; M. Porrmann
Sponsor(s): IEEE CSP
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Bialystok, Poland
Conference Date: 13 September 2006
Page(s): 214 - 219
ISBN (Paper): 0-7695-2554-7
DOI: 10.1109/PARELEC.2006.36
Regular:

Dynamically reconfigurable FPGAs are well known to combine the flexibility of software with the performance of application specific hardware. As such they can be used as powerful but still... View More

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