IEEE - Institute of Electrical and Electronics Engineers, Inc. - A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): Hyung-Rok Lee ; Ook Kim ; Keewook Jung ; J. Shin ; Deog-Kyoon Jeong
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 2,402 - 2,411
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696304
Regular:

A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter... View More

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