IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Clock Duty-Cycle Correction and Adjustment Circuit

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): J.S. Humble ; P.J. Zabinski ; B.K. Gilbert ; E.S. Daniel
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 2,132 - 2,141
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696273
Regular:

A clock duty-cycle correction circuit that accepts input duty cycles ranging from 30% to 70% and maintains a user-selectable output duty cycle over a frequency range of 500MHz to 6GHz is... View More

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