IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): Y. Nitta ; Y. Muramatsu ; K. Amano ; T. Toyama ; J. Yamamoto ; K. Mishina ; A. Suzuki ; T. Taura ; A. Kato ; M. Kikuchi ; Y. Yasui ; H. Nomura ; N. Fukushima
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 8
Page(s): 2,024 - 2,031
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696261
Regular:

A progressive 1/1.8-inch 1920times1440 CMOS image sensor with a column-inline dual CDS architecture uses a 0.18mum CMOS process. This sensor implements digital double sampling with analog CDS on a... View More

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