IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): Chang-Hyo Yu ; Kyusik Chung ; Donghyun Kim ; Lee-Sup Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 1,606 - 1,615
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696215
Regular:

A 3D vertex processor with a floating-point 4-threaded and 4-issue VLIW architecture and a TnL vertex cache is implemented for mobile multimedia applications in a 0.18mum 4M CMOS process. The... View More

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