IEEE - Institute of Electrical and Electronics Engineers, Inc. - Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): S. Tam ; J. Leung ; R. Limaye ; S. Choy ; S. Vora ; M. Adachi
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 1,512 - 1,521
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696202
Regular:

The clock generation and hybrid clock distribution for a dual-core Xeonreg processor with 16MB L3 cache are designed for <11ps global clock skew in a 435mm2 die. The cache and... View More

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