IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 2.5Gb/s Multi-Rate 0.25/spl mu/m CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): M.H. Perrott ; Yunteng Huang ; R.T. Baird ; B.W. Garlepp ; Ligang Zhang ; J.P. Hein
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 1,276 - 1,285
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696175
Regular:

A CDR comprises a Hogge detector and a 1st-order DeltaSigmaADC, and uses a hybrid analog/digital loop filter to enhance integration and allow bandwidth tuning over a wide range of data... View More

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