IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): Y. Shimizu ; S. Murayama ; K. Kudoh ; H. Yatsuda ; A. Ogawa
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 802 - 811
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696120
Regular:

A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process. It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback amplifier. ENOB is 10.2b at a 0.7V... View More

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