IEEE - Institute of Electrical and Electronics Engineers, Inc. - A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): M. Brox ; H. Fibranz ; M. Kuzmenka ; F. Lu ; S. Mann ; M. Markert ; U. Mbller ; M. Plan ; K. Schiller ; P. Schmblz ; P. Schrbgmeier ; A. Tauber ; B. Weber ; P. Mayer ; W. Spirkl ; H. Steffens ; J. Weller
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 537 - 546
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696090
Regular:

A 512Mb DRAM operates up to a data-rate of 2Gb/s/pin. It employs an averaging pad-driver design which reduces simultaneous switching noise to one third of a conventional design. Resistive damping... View More

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