IEEE - Institute of Electrical and Electronics Engineers, Inc. - An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme

2006 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

Author(s): Kyu-hyoun Kim ; Uksong Kang ; Hoe-Ju Chung ; Duk-Ha Park ; Woo-Seop Kim ; Young-Chan Jang ; Moonsook Park ; Hoon Lee ; Jin-Young Kim ; Jung Sunwoo ; Hwan-Wook Park ; Hyun-Kyung Kim ; Su-Jin Chung ; Jae-Kwan Kim ; Hyung-Seuk Kim ; Kee-Won Kwon ; Young-Taek Lee ; Joo Sun Choi ; Changhyun Kim
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: San Francisco, CA, USA
Conference Date: 6 February 2006
Page Count: 10
Page(s): 527 - 536
ISBN (Paper): 1-4244-0079-1
ISSN (Paper): 0193-6530
DOI: 10.1109/ISSCC.2006.1696089
Regular:

A 288Mb deca-data rate SDRAM with an I/O error-detection scheme is developed. Deca-data rate is proposed to include CRC for the higher data-rate beyond 5Gb/s/pin using a conventional DRAM process.... View More

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