IEEE - Institute of Electrical and Electronics Engineers, Inc. - Automatic decomposition for sequential equivalence checking of system level and RTL descriptions

Proceedings. Fourth ACM & IEEE International Conference on Formal Methods and Models for Co-Design. (MEMOCODE'06)

Author(s): S. Vasudevan ; J.A. Abraham ; V. Viswanath ; Jiajin Tu
Sponsor(s): ACM SIGon Design Auto.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Napa, CA, USA
Conference Date: 27 July 2006
Page Count: 10
Page(s): 71 - 80
ISBN (Paper): 1-4244-0421-5
DOI: 10.1109/MEMCOD.2006.1695903
Regular:

Sequential equivalence checking between system level descriptions of designs and their register transfer level (RTL) implementations is a very challenging and important problem in the context of... View More

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