IEEE - Institute of Electrical and Electronics Engineers, Inc. - Should Logic SER be Solved at the Circuit Level?

12th IEEE International On-Line Testing Symposium

Author(s): T.M. Mak ; S. Mitra
Sponsor(s): IEEE Comput. Soc.
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Lake Como, Italy
Conference Date: 10 July 2006
Page(s): 199
ISBN (Paper): 0-7695-2620-9
DOI: 10.1109/IOLTS.2006.56
Regular:

SER is one of the problems associated with continued scaling. Traditionally, logic SER is solved at the system/architecture level (e.g., DMR, TMR, checkpointing/recovery). There has also... View More

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