IEEE - Institute of Electrical and Electronics Engineers, Inc. - Reducing the associativity and size of step caches in CRCW operation

Proceedings. 20th International Parallel and Distributed Processing Symposium

Author(s): M. Forsell
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Rhodes Island, Greece
Conference Date: 25 April 2006
ISBN (Paper): 1-4244-0054-6
DOI: 10.1109/IPDPS.2006.1639546
Regular:

Step caches are caches in which data entered to a cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded architecture they can... View More

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