IEEE - Institute of Electrical and Electronics Engineers, Inc. - A Case for MLP-Aware Cache Replacement

Proceedings. 33rd International Symposium on Computer Architecture

Author(s): M.K. Qureshi ; D.N. Lynch ; O. Mutlu ; Y.N. Patt
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Boston, MA, USA
Conference Date: 17 June 2006
Page(s): 167 - 178
ISBN (Paper): 0-7695-2608-X
ISSN (Paper): 1063-6897
DOI: 10.1109/ISCA.2006.5
Regular:

Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache misses in parallel... View More

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