IEEE - Institute of Electrical and Electronics Engineers, Inc. - High-throughput decoder for low-density parity-check code

Proceedings of the ASP-DAC 2006. Asia and South Pacific Design Automation Conference 2006

Author(s): T. Ishikawa ; K. Shimizu ; T. Ikenaga ; S. Goto
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Yokohama, Japan
Conference Date: 24 January 2006
Page Count: 2
ISBN (Paper): 0-7803-9451-8
DOI: 10.1109/ASPDAC.2006.1594662
Regular:

We have designed and implemented the LDPC decoder chip with memory-reduction method to achieve high-throughput and practical chip size. The decoder decodes (3,6)-2304 bit regular LDPC codes using... View More

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