IEEE - Institute of Electrical and Electronics Engineers, Inc. - Deterministic low-latency data transfer across non-integral ratio clock domains

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): S. Balasubramanian ; N. Natarajan ; O. Franza ; C. Gianos
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.71
Regular:

System on a chip (SOC) implementations typically require their functional blocks to run at different clock frequencies in order to better optimize the system performance for a wide variety of... View More

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