IEEE - Institute of Electrical and Electronics Engineers, Inc. - Symbolic time-domain behavioral and performance modeling of linear analog circuits using an efficient symbolic Newton-iteration algorithm for pole extraction

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): R. Chakraborty ; M. Ranjan ; R. Vemuri
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.153
Regular:

Symbolic modeling techniques employ behavioral models to capture the input-output relationships of linear(ized) analog circuits in conjunction with performance models to measure performance... View More

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