IEEE - Institute of Electrical and Electronics Engineers, Inc. - Generating scalable polynomial models: key to low power high performance designs

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): G. Girishankar ; S. Tiwari
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.94
Regular:

As the need for power reduction techniques based on on-chip dynamic voltage scaling is on the rise, a design flow that can take full advantage of the performance/power tradeoffs is required. In... View More

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