IEEE - Institute of Electrical and Electronics Engineers, Inc. - Exceptional ASIC: through automatic timing exception generation (ATEG)

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): S. Embanath ; V. Ramakrishnan
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.86
Regular:

The next inclusion in the industrial ASIC design flow is going to be automatic timing exception generation (ATEG). The current manual and reactive approach of identifying timing exceptions and... View More

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