IEEE - Institute of Electrical and Electronics Engineers, Inc. - Performance measurement and improvement of asymmetric three-tr. cell (ATC) DRAM toward 0.3V memory array operation

Proceedings. 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems and Design

Author(s): M. Ichihashi ; H. Toda
Publisher: IEEE - Institute of Electrical and Electronics Engineers, Inc.
Publication Date: 1 January 2006
Conference Location: Hyderabad, India, India
Conference Date: 3 January 2006
ISBN (Paper): 0-7695-2502-4
ISSN (Paper): 1063-9667
DOI: 10.1109/VLSID.2006.132
Regular:

For a Mb-class embedded memory, asymmetric three-transistor cell (ATC) DRAM has been reported. The memory cell is a non-destructive-read type and the memory array runs at 0.5V, half the... View More

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